| 摘要 |
PURPOSE:To execute an arithmetic operation of a URR number without deteriorating the performance of the arithmetic operation, by adding an alternate route to a data transfer path, providing an exponential part computing element, and extending the bit width of the computing element of a mantissa of the URR number. CONSTITUTION:In case of subtraction, a mantissa having a large exponent is allowed to take a complement by a T/C circuit 12, and thereafter, when that which has taken the complement is a mantissa of a first operand, a complement is taken again with respect to the sum of the mantissas in a mantissa adder 14. An output of the mantissa adder 14 calculates a shift number so that a result of shift by a post-shifter 18 satisfies a format of the mantissa which has been separated, by a zero checking circuit 15, a result of a correction by the shift number, which has been executed to a large exponent by a URR number (floating point number) use exponential part updating computing element 16 is set to a URR number use exponential part arithmetic operation result register 19, and also, the mantissa of URR which has been normalized is set to a mantissa arithmetic operation result register 21. Thereafter, said number is converted so as to satisfy numerical expression format of URR by a URR number exponential part and mantissa coupling circuit 22, and stored in a floating point register 2 or a memory. |
