| 摘要 |
PURPOSE:To restore the output clock phase into the stable state even if the relation of phase is critical by providing a circuit detecting the critical phase relation between the output clock and a synchronizing signal and controlling a frequency division circuit obtaining the output clock by the output of the said circuit. CONSTITUTION:A flip-flop(FF) 103 counts an even/odd number of output clocks CLK3. A FF 104 frequency-divides a clock CLK 2 regulating an internal timing and outputs the output clock CLK3. An AND gate 105 constitutes a jitter detection section 110 detecting the critical phase relation with the output clock CLK3 and the synchronizing clock CLK1 together with the FF 103. Through the constitution above, if the phase of the synchronizing signal CLK1 is led or lagged, the Q output of the FF 103 goes to '1', the output of the AND gate 105 goes to '1' only once at the leading of the signal CLK1 to control the frequency division FF 104 thereby inverting the phase of the output clock CLK3 by 180 deg.. Thus, when the clocks CLK1, 3 reach the critical phase relation, the phase of the output clock is switched to eliminate the state and the switching is executed with the Q output only by shifting the trailing phase of the Q output of the FF, then even if the titled circuit is used for applications offering tight pulse requirements, an output clock having a constant delay and pulse width without incurring any malfunction. |
