| 摘要 |
PURPOSE:To reduce noise generated at a connecting point of each component or the like by constituting the titled circuit by 1st and 2nd delay circuits and 1st-4th logic circuit, and holding the output of a signal of a prescribed level for a prescribed time corresponding to the 1st identification pulse signal outputted from the 3rd logic circuit to decrease the number of components. CONSTITUTION:The 1st capacitor 3 of a 1st delay circuit 2 is charged/discharged by the ON/OFF operation corresponding to an signal of a 1st transistor (TR) 1, an output of a 1st delay circuit 2 is outputted from a 3rd logic circuit 9 via a 1st logic circuit 6 to operate the 2nd TR 10, a 2nd capacitor 13 of a 2nd delay circuit 11 is charged/discharged by the operation of the 2nd TR 10 and an output signal outputted by the discharge of the 2nd capacitor 13 is inverted by the 4th logic circuit 14 ands the result is outputted. Thus, the pulse having a desired pulse width is identified and the output of the identification signal is held for a prescribed period.
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