| 摘要 |
PURPOSE:To assure the order of memory access and to secure fast memory access processing by setting a waiting mode while an address having a memory access request is used and transmitting with priority said address in response to the processing order when a bank desirous to access is available. CONSTITUTION:The counter circuits 71-74 of an access control circuit correspond to four address registers and have the count values 0-31 in accordance with the transmitting state of memory access requests. The count value 0 shows that effective addresses are not taken by four corresponding registers 1-4 and therefore addresses can be fetched by these registers. Gate circuits 75-78 receive the count values of the circuits 71-74 via data lines 101-104 and coincidence signals of banks via data lines 16-19. Then 0 is delivered via data lines 105-108 when banks are coincident with each other (busy mode of bank); while the count values of circuits 71-74 are delivered as they are via the lines 105-108 in case the banks are not coincident with each other (non-busy mode of bank). Thus those count value are supplied to a switch control circuit 79. Here the smaller the count value the higher the priority.
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