发明名称 AMPLITUDE LIMIT CIRCUIT
摘要 PURPOSE:To completely suppress the phase fluctuation of an output signal by connecting a parallel circuit comprising a resistor and a capacitor to each emitter of a differential pair transistor (TR) and using a variable capacitor as the capacitor. CONSTITUTION:Junction capaitors 17, 18 are used as variable capacitors. The capacitance of the junction capacitors 17, 18 changes depending on a reverse bias voltage. A voltage drop appearing across the resistors 3, 4 is used as a reverse bias voltage device. The voltage drop is changed freely by varying the current flowing to the resistors 3, 4. Thus, a constant current source 41 whose constant current is varied is used as the constant current source, a constant current I' to obtain an optimum capacitance is searched and the current is fixed to the value I'.
申请公布号 JPS62271511(A) 申请公布日期 1987.11.25
申请号 JP19860113606 申请日期 1986.05.20
申请人 FUJITSU LTD 发明人 KITASAGAMI HIROO;AMAMIYA IZUMI;KAWAI MASAAKI
分类号 H03G11/00 主分类号 H03G11/00
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