| 摘要 |
PURPOSE:To reduce the number of terminals and to decrease the supplies of a fixed logic level by supplying an external clock signal to a clock terminal or applying a constant voltage thereto to be commonly used for two purposes. CONSTITUTION:When an alteration to a test mode is desired to stationarily supply logic '0'. to clock terminals X1, X2, both first clock signal CL1 and second clock signal CL2 are fixed to the logic '0', and the outputs P1, P2 of inverters 4, 5 are reversely fixed to logic '1'. As a result, the output of an AND circuit 6 is fixed to the logic '1', and the output of an inverter 7 is fixed to the logic '0', the outputs of AND circuits 8, 9 are inverted to set a reset signal RS to logic '0', and a latch signal LTC to logic '1'. Accordingly, a latch circuit 15 latches a test signal to be supplied to a signal input terminal to be supplied to a decoder 16, thereby an making internal circuit function in a test mode.
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