| 摘要 |
PURPOSE:To decrease the power consumption and to facilitate the integration of the titled circuit by reducing the load per circuit and the distributed resistor and distributed capacitance of an output control line. CONSTITUTION:When a clock signal 121 is in a high level and a load signal 120 is in a high level, storage nodes 290 and 283 come in the voltage level equal to an input signal from an input data bus 101, and a new value is loaded on the nodes 290 and 283. When a signal 101 is in a low level and an output control signal 109 comes in a high level, charges are accumulated in a node 281 causing a bootstrap action to be executed at the leading edge of the signal 121. If the node 281 is in a high level during the immediately preceding action cycle, a switch 246 is operated via a switch 245 at the leading edge of the signal 121 to discharge an output bus 103. By such a constitution, the power consumption is reduced and the circuit integration is facilitated. |
