| 摘要 |
PURPOSE:To realize a simplified pattern layout and to enhance integration by a method wherein driver MESFETs and load MESFET are equal to each other in gate width. CONSTITUTION:A load MESFET 11 and driver MESFETs 12, 13 constituting a logical stage are equal to each other in gate width. For example, the gate, width Wg=10mum and gate length Lg=1mum, meaning Wg/Lg is 10/1 in both load MESFET and pull-down MESFET. This design suppresses the current capacity of the pull-down MESFET as low as possible for the ensurance of low power consumption and improved fan-out characteristics. The ratio of the current drive capacity IL of the load MESFET 11 to the current drive capacity ID of the driver MESFETs 12, 13 in the ON state may be desirably set in spite of the same gate width. The level shift diode junction area will be enlarged for the sustenance of high speed features. |
