发明名称 PSEUDO NORMAL TEST SYSTEM FOR FREQUENCY FAULT DETECTING CIRCUIT
摘要 PURPOSE:To allow a frequency fault detecting circuit to confirm the normality of an oscillating circuit easily by adding an oscillating frequency fluctuation circuit possible for external control to the oscillating circuit. CONSTITUTION:The oscillating circuit 20 has the oscillating frequency fluctuation circuit 20A in addition to an oscillating circuit element and when a switch SWO is interrupted, an output of the same frequency fo as an input signal frequency fi is generated and transmitted. When the switch SWO is connected by a switch control signal, the oscillating circuit 20 becomes a circuit including a capacitor C2 and generates a signal in frequency fi+DELTAf. The frequency fault detecting circuit 30 compares a difference DELTAf between the said frequency and the input frfequency fi with a standard value fs, and when DELTAf>fs, an alarm ALM is given to a pseudo normality test control cricuit 40 as a value out of the standard value. The capacitor C2 is selected so as to form the relation of DELTAf>fs when the capacitor is inserted to the oscillating circuit 20. Thus, when the switch SWO is turned on from the control circuit 40, if no alarm ALM is obtained, it is discriminated that the detecting circuit 30 is faulty.
申请公布号 JPS6019324(A) 申请公布日期 1985.01.31
申请号 JP19830126064 申请日期 1983.07.13
申请人 HITACHI SEISAKUSHO KK 发明人 OGURI YOUZOU
分类号 H03B1/00;G06F1/04;H03L7/095;(IPC1-7):H03L7/08 主分类号 H03B1/00
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