| 发明名称 |
METHOD FOR FABRICATING IGFET INTEGRATED CIRCUITS |
| 摘要 |
A rapid and systematic method for performing chip layout of a random-logic IGFET circuit includes steps for arranging the device features and interconnection features corresponding to the circuit in respective positions in an array of intersecting rows and columns. The method provides layouts of device and interconnection features having a high packing density and a high degree of order and regularity to facilitate checking for layout errors. |
| 申请公布号 |
DE3072027(D1) |
申请公布日期 |
1987.10.15 |
| 申请号 |
DE19803072027 |
申请日期 |
1980.10.15 |
| 申请人 |
WESTERN ELECTRIC COMPANY, INCORPORATED |
发明人 |
LAW, HONG-FAI STEPHEN;LOPEZ, ALEXANDER DIAZ |
| 分类号 |
C07C39/373;B01J27/08;C07C27/00;C07C37/00;C07C67/00;H01L21/768;H01L21/822;H01L21/8234;H01L23/528;H01L27/04;H01L27/088;H01L27/10;H01L27/112;H01L29/78;(IPC1-7):H01L21/72 |
主分类号 |
C07C39/373 |
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