| 摘要 |
<p>PURPOSE:To reduce the number of times of patterning by once by executing the patterning of a gate electrode formed on a semiconductor layer consisting of a thin film transistor (TR) to be a non-linear element through an insulating layer simultaneously with the patterning of lower insulating and semiconductor layers. CONSTITUTION:A Cr layer 13 and an n<+>a-Si layer 14 obtained by doping phosphorus at high density are laminated on a glass base on which a picture element electrode 21 and a row electrode 22 are previously formed by using a transparent conductive film. Then, a source electrode 3 and a drain electrode 4 are patterned by using photorithography. A non-doped a-Si layer 5, a SiN layer 6 and a Cr layer 7 are successively laminated on the electrodes 3, 4. Then, the Cr layer 7, the SiN layer 6 and the a-Si layer 5 are successively patterned only by one resist formation and a thin film TR 10 having a gate electrode 71 is completed. A line electrode 72 is also constituted of a semiconductor layer 5, an insulating layer 6 and a conductive layer 7 and these layers are simultaneously patterned.</p> |
