| 摘要 |
PURPOSE:To eliminate one clock that is additional for purposes of the interpretation of a port-width response signal and the relocation of a data block by providing an address discriminating means and a port-width holding means. CONSTITUTION:An address discriminating circuit 111 as the address discriminating means, discriminates to what area the physical address on an address bus 104 corresponds, and outputs the result of the discrimination as an address are information 113. A port-width holding register 112 as the data-bus port-width information holding means, holds the information of the width port for data-bus for a memory device or a peripheral equipment in each physical address space. The content of the register 112 is able to be written in or read out. The register 112 also outputs the data-bus port-width of a memory device or a peripheral equipment programmed in correspondent area as a port-width information 121 at the time when an address area information 113 is inputted. |
