| 摘要 |
This distributed constant type delay line has an inductance element which has a plurality of main portions lying generally in parallel stacked planes. Each of the main portions has a conducting portion with a generally central line, the conducting portions being connected in series with one another with their the central lines lying generally parallel to one another and being alternately staggered to and fro in the direction generally perpendicular to them and generally parallel to the stacked planes. A ground electrode is interposed between the conducting portions of two neighboring ones of the main portions of the inductance element. And a dielectric layer is interposed between the ground electrode and a neighboring one of the main portions of the inductance element. Thereby, a very efficient and compact construction becomes available, which is suitable for being made as a chip. Optionally, capacitance compensating electrodes are defined as extending out from the main portions of the inductance element.
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