| 摘要 |
A process for forming n- and p-wells (90, 88) in a semiconductor substrate (76) wherein each well (88, 90) has a shallow, highly-doped surface layer (92, 96) whose depth may be independently controlled. This high/low doping profile for a twin well CMOS process may be produced using only one mask level. The method provides high/low impurity profiles in each well (88, 90) to optimize the NMOS and PMOS active transistors; provides close NMOS to PMOS transistor spacing; avoids a channel-stop mask level and avoids a threshold adjustment/punchthrough mask level. |
