| 摘要 |
<p>In association with memory arrays of a memory subsystem of a data processing system, apparatus is disclosed for selecting a group of address signals to be applied to a memory array and for applying the address signals to the memory array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the latch is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage device for the period of time necessary to utilize the memory array. The role of the uncertainty or skew in requiring the multiplicity of signals is discussed.</p> |
