发明名称 OUTPUT CONTROL SYSTEM
摘要 PURPOSE:To eliminate an instruction conventionally given to a save-register to let it save by constituting an output port and the save-register to save the content of the output port in the same address. CONSTITUTION:When a processor 1 addresses the output port 11, the save- register 10 also can be addressed by an address decoder 13 by using address informations AD 11-0. By writing in the output port 11, the same data can be saved in the register 10. Accordingly, output steps are simplified as of reading from the output port, operating the bit, writing in the output port. Meanwhile, since an address decoder 8 is a one to select a RAM 9, RAM areas other than that the register 10 can be optionally addressed by means of the 12-bits of AD 11-0.
申请公布号 JPS62162158(A) 申请公布日期 1987.07.18
申请号 JP19860002961 申请日期 1986.01.10
申请人 FUJITSU LTD 发明人 HASEGAWA KENICHI
分类号 G06F9/46;G06F9/48;G06F13/14 主分类号 G06F9/46
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