发明名称 TEST CONTROLLING SYSTEM FOR ARITHMETIC PROCESSOR
摘要 PURPOSE:To efficiently use memory area of a main memory by detecting stall state of a test and incorporating the memory area of a main memory separated from an operating system in the operating system when stalled. CONSTITUTION:When starting of a test is instructed to a test controller 14, an operating system cuts of a memory area for test logically. In case the test controller 14 did not receive a notice that the test is in execution or that the test is terminated within a time T2 after the device started the test or after receiving the notice that the test is in execution, the test controller 14 regards that the test is stalled, and stops an arithmetic processing unit B 11 which is in testing through a test controlling interface B16, and requests incorporation of a memory area for test to the operating system through a test controlling interface A15 and an arithmetic processing unit A11. Thereby, the memory area for test cut off logically is incorporated in the operating system, and the test is terminated.
申请公布号 JPS62127946(A) 申请公布日期 1987.06.10
申请号 JP19850268671 申请日期 1985.11.29
申请人 NEC CORP 发明人 MIKOYAMA SHIGEZO
分类号 G06F11/22;G06F7/38 主分类号 G06F11/22
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