ERRONEOUS PULSE SEQUENCE DETECTOR

摘要

The absence or addition of a pulse is detected by using a three-stage shift register capable of shifting bidirectionally. A 'O' is loaded into the first stage and a '1' into the third stage of the register. The 'O' is shifted toward the third stage with one pulse therein. An error signal is generated respondingly as the similar outputs from the first and third stages are detected. The detecting and generating steps include inverting the output of the first stage and NANDing the inverted output with the output of the third stage.