发明名称 BIT PATTERN GENERATOR
摘要 PURPOSE:To set many patterns with a simple circuit by providing an address generation means generating a time series of an address data by a pattern possible for setting change and a storage means inputting the said data and outputting a bit pattern as the time series. CONSTITUTION:A binary-coding 2<n>-adic counter 1 inputs a clock signal CL and outputs count data D1n...D13.D12.D11 being an n-digit binary data. n-Set of setting circuits 2 input data D1i (i=1-n) and a control signal Si and output a data D2i. The data D2i is the data D1i, its inverse or a voltage signal V of logical value '0'. A ROM 3 is a ROM of 2<n>-wordX1-bit constitution, the address is designated by the address data D2i being an n-digit binary data as above to read an output data D0. A bit pattern is written sequentially to each address of the ROM 3. In changing control signals S1-Sn, one string bit pattern different therefrom is generated.
申请公布号 JPS62120747(A) 申请公布日期 1987.06.02
申请号 JP19850261778 申请日期 1985.11.20
申请人 NEC CORP 发明人 MORIMOTO HIDEAKI
分类号 H04L9/22 主分类号 H04L9/22
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