| 摘要 |
PURPOSE:To facilitate the adjustment and change of a delay time by connecting a capacitor between an output terminal of an inverter and a power terminal or a ground terminal so a to adjust the delay time. CONSTITUTION:Since the gate width of a transistor (TR) 11 is formed sufficiently smaller than that of a TR 10, when an input signal 7 rises from L to H, the capability of the TR 11 discharging an electric change stored in capacitors 12, 13 to a ground potential is small and the waveform at an output 8 descends slowly. Thus, the level at an output terminal 9 starts rising after the level of the waveform at the output 8 reaches a threshold value 16 of the 2nd stage inverter (at a point of time 17), and a time delay 18 is caused in comparison with the leading of the input signal 7. |
