| 摘要 |
<p>A field-effect transistor device comprising a p-type silicon substrate (54), a pair of n-channel MOS transistors (Q1, Q2), and a wiring means connecting the MOS transistors. The first MOS transistor (Q1) has a gate electrode (52A) provided above the substrate (54) and extending in one direction, and two regions (56A, 56B) formed in the substrate (54), located on two opposing sides of the gate electrode (52A), and serving as a source and a drain. The second MIS transistor (Q2) has a gate electrode (52B) provided above the substrate (54) and extending in said one direction, and two regions formed in the substrate (54), located on two opposing sides of this gate electrode (52B), and serving as a source and a drain. The wiring means includes bit lines BL and BL which permit the source-drain paths of the first and second MIS transistors (Q1, Q2) to be oriented in the same direction.</p> |
