| 摘要 |
PURPOSE:To avoid the output of an erroneous alarm even in case reading access is given to a memory space where no writing action is performed, by setting correctly a parity bit for all spaces of a RAM immediately after a CPU is reset. CONSTITUTION:A CPU 10 sets a memory parity bit writing end signal 17b at 0 immediately after a reset mode and then reads the data on a RAM 12 for each word to write it again on the RAM 12. This action is performed for all spaces of the RAM 12. Thus the parity bit of the RAM 12 is written on a parity bit memory RAM 14 through a parity generating circuit 13 by carrying out the above-mentioned action. Then the CPU 10 sets the signal 17b at 1 and activates a parity check circuit 15.
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