发明名称 METHOD FOR CHECKING MASK PATTERN
摘要 <p>PURPOSE:To shorten the time required for mast pattern checking by grouping the extracted transistor circuits so that a transistor group constituting one logical gate becomes one group, and thereafter converting the connections of the transistors within each group to logical gates. CONSTITUTION:In tracing the connections for grouping transistors, the class of the equipotential portion of the wiring portion of each transistor circuit is first determined. After the class of each node is thus determined, the transistors are traced and grouped. Since the connections of the transistors are traced and the transistor circuits are grouped so that a transistor group constituting one logical gate becomes one group, without recognizing whether the transistor connection is serial or parallel as has conventionally been done, it is easy to recognize and convert the connections of the transistors within each group into logical gates later on, thereby enabling the time required for conversion into logical gate level circuits to be shortened.</p>
申请公布号 JPS6288323(A) 申请公布日期 1987.04.22
申请号 JP19850229535 申请日期 1985.10.15
申请人 FUJITSU LTD 发明人 OE RYOICHI
分类号 G01N21/88;G01N21/956;G03F1/00;G03F1/84;G06F17/50;G06K9/00;H01L21/027;H01L21/30;H01L21/66 主分类号 G01N21/88
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