INTEGRATED CIRCUIT WITH STRESS ISOLATED HALL ELEMENT

摘要

INTEGRATED CIRCUIT WITH STRESS ISOLATED HALL ELEMENT A silicon integrated circuit includes a centrally located Hall element having an annular moat region surrounding the Hall element to isolate it from built-in stresses in adjacent parts of the IC. The moat comprises at least one annular isolation wall, but preferably two concentric isolation walls. This moat construction also leads to a reduction in dependency of Hall element symmetry upon process variables.