| 摘要 |
PURPOSE:To reduce current consumption for writing operation, by applying a signal, which has different voltage levels for reading operation and writing operation, in series to load transistors (TR) of transistor logical gates constituting the decoder of a memory control circuit. CONSTITUTION:Between a power source Vcc and the drain of the load TR1 of a decoder circuit composed of E/D type MOSTRs, a depletion type field effect TR5 is connected in series. The gate of the TR5 is connected to a control signal S. The control signal S has logic ''1'' during the reading operation of the decoder circuit and logic ''0'' during the writing operation. The depletion type TRs are normally turned on and the current of each TR varies with its gate voltage. Mutual conductance gm is 2k(VGS-VT), where (k) is a proportional constant determined by the structure of the TRs, and a current IDS flowing through the depletion type TRs is gm<2>/4k. For this purpose, when the control signal S has the ''1'', the current is flowed more and when the ''0'', the current is reduced. |
