| 摘要 |
PURPOSE:To ensure stable circuit operation even when a large transient current flows to the chip inside by giving a source power voltage whose level is controlled in correspondence to its operating characteristic to a MOS transistor (TR) circuit section. CONSTITUTION:A circuit 1i (11, 12,... 1i,..., 1n) is a n stage of clock generating circuit. Voltages VDD and VSS are respectively drain and source power supply voltages supplied from a chip external terminal. No voltage VSS is fed directly to a source power voltage terminal 3 of the clock generating circuit 1i, a power voltage converting circuit, in this case a base bias generating circuit 2 in this case, is used and its output VBB is fed to a source power voltage terminal 3. A MOS TR Q1 as a switch element controlled by a clock phiS generated by the internal circuit and MOS TRs Q2-Q4 as level shift circuits are inserted in series between an output terminal of the base bias generating circuit 2 and the source power voltage terminal 3 of the clock generating circuit 1i. |
