| 摘要 |
Circuit in which complementary current levels are used in order to limit the voltage to two reference values (Uref1 and Uref2). An additional limiting transistor (16, 26) is connected to each of the output transistors (12, 22) connected with the signal line (S), in parallel with the base-emitter section. In the event of interference the relevant limiting transistor (16; 26) takes charge of the majority of the current needed in order to limit the voltage. The limiting transistors (16; 26) have larger emitter surfaces than the current level transistors so that the pre-current continually imprinted by means of the current sources (15; 25) can be very small. The continual pre-current substantially improves the dynamic behaviour of the overall circuit and the limiting transistors (16, 26) significantly reduce the power loss and space requirements.
|
