| 摘要 |
PURPOSE:To suppress the oscillation phenomenon of a voltage detector by inserting a constant current circuit into the CMOS inverter of the output part of the detector and stopping a through current from flowing. CONSTITUTION:When an input voltage VIN is applied between terminals 7 and 8, a reference voltage VREF is developed at the output point A of a reference voltage generating circuit 1. The resistance divided voltage VB of the voltage VIN is generated at the connection point B between resistances 2 and 3 and the voltages VREF and VB are inputted to a comparator 4, thereby outputting a VSS level to an output point C when VB>VREF or a VDD level when VB<VREF. When a detection voltage with which the output of the comparator 4 is inverted is VDET, the VDD level is outputted to a voltage detection signal output terminal 9 when VIN>VDET and the VSS level is outputted when VIN<VDET. For the purpose, high impedance is interposed between a power source and the voltage detector and the voltage drop by the impedance is set to a voltage value which does not exceeds the hysteresis width of the detection voltage VDET of the comparator, so that oscillations due to an excessive through current are suppressed.
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