| 摘要 |
PURPOSE:To execute ordinary processing while waiting for individual processor by providing plural processors to make parallel processing and providing independent timer in each processor. CONSTITUTION:N (8 units) of processors are provided in a parallel processor controller 412. As the longest execution time of a CPU 20 that makes general processing is 4musec, '4' is put in a counter and bus acquisition is waited for. When acquired, a ROM 203 is accessed by address value to each processor in a dual port RAM 411 and instruction is read. As the instruction of a parallel processor is made to 2 byte fixed length, it can be fetched within a fixed time (1Xsec). Time is adjusted to make the counter '0', data are processed and time is adjusted to make to 8mus as a whole, and then (n) for designating processor is changed, and above-mentioned procedure is repeated. |
