发明名称 CMOS bias voltage generating circuit
摘要 A bias generating circuit for reducing an external DC power supply voltage to a predetermined, lower, stable DC voltage used as a power source for internal logic circuits in a semiconductor IC chip includes an oscillator for converting the external DC voltage into a pulse signal, a smoothing circuit for converting a pulse signal into the lower DC voltage, and a control circuit interposed between the oscillator and the smoothing circuit for varying the pulse duration of the pulse signal from the oscillator to a changed pulse signal, and for regulating the lower DC voltage to a predetermined amplitude in response to the voltage variation in the lower DC voltage. The control circuit comprises a CMOS inverter, a CMOS buffer circuit for varying the pulse duration of the output signal of the CMOS inverter, and a voltage compensating circuit for controlling the transconductance of the CMOS inverter in response to the variation of the lower DC voltage.
申请公布号 US4638184(A) 申请公布日期 1987.01.20
申请号 US19840650408 申请日期 1984.09.13
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 KIMURA, KIKUO
分类号 G11C11/413;G05F1/46;G11C11/407;H01L21/822;H01L27/04;H02M3/155;H03F1/30;(IPC1-7):G05F1/56 主分类号 G11C11/413
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