| 摘要 |
PURPOSE:To access a main memory even during a transfer mode by switching a bank to the submemory side at the transfer of information to an information storage means, and at the intermission of transfer, switching the bank to the main memory side. CONSTITUTION:When direct memory access (DMA) transfer is intermitted, a DMA controller 5 stops the output of a DAM permission signal L2 and also stops the output of a bank switching signal L3. Thereby, the output of an inverter 18 is turned to the 'H' level, the bank is switched to the main memory 2 and a buffer 14 is opened. Since the output of a hold permission signal L1 from a CPU 1 is also stopped, buffers 13, 15 are opened. Consequently, the CPU 1 can supply address data to the main memory 2 through the buffer 13 and can receive the data from the main memory 2 through the buffers 14, 15. Thus, the CPU 1 can access all areas of the main memory 2 at the intermission of DMA transfer.
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