| 摘要 |
PURPOSE:To always execute a transfer of data and to simplify data transfer control program by starting a program for executing a data transfer processing, by an interruption of a transmitting buffer idle/busy state signal of a USRT or a result of a collation of a USRT status data, and executing a transmission processing at the time of this start. CONSTITUTION:An interruption control circuit 3 is provided with a processor 1 containing a program 4 for performing a data transfer control, a transmitting buffer 21, a transmission/reception control circuit 22, a USRT 2 containing a receiving buffer 23, an interruption register 31, and an interruption mask register 32. Also, an address bus 101 is connected to each element from the processor 1, a transmitting signal line 102 is connected to an external device from the USRT 2, a receiving signal line 103 is connected to the USRT 2 from the external equipment, and also a transmitting buffer idle/busy state signal line 104 and a receiving buffer idle/busy state signal line 105 are connected to the interruption control circuit 3. Furthermore, an interruption signal line 106 is connected to the processor 1 from the interruption control circuit 3.
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