发明名称 |
Semiconductor memory device |
摘要 |
A semiconductor memory device including a first MIS transistor having source and drain regions formed in a substrate and a gate electrode provided on the substrate through an insulating layer; a semiconductor layer provided on the first MIS transistor through the insulating layer and being in contact with the source and drain regions of the first MIS transistor; a second MIS transistor having source and drain regions formed in the semiconductor layer and being in contact with the source and drain regions of the first MIS transistor and having a gate electrode provided on the semiconductor layer through an insulating layer; and a bit line being in contact with the source or drain region of the second MIS transistor and extended on the second MIS transistor; each gate electrode of the first and the second MIS transistors being connected with different word lines respectively, and impurities having an amount more than a required value being doped to at least one of the substrate and the semiconductor layer below the gate electrode of the first MIS transistor and the semiconductor.
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申请公布号 |
US4630089(A) |
申请公布日期 |
1986.12.16 |
申请号 |
US19840654701 |
申请日期 |
1984.09.26 |
申请人 |
FUJITSU LIMITED |
发明人 |
SASAKI, NOBUO;SUZUKI, YASUO |
分类号 |
G11C17/08;H01L21/822;H01L21/8246;H01L27/06;H01L27/10;H01L27/112;H01L29/78;(IPC1-7):H01L29/78;G11C17/00;H01L27/02;H01L29/04 |
主分类号 |
G11C17/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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