| 摘要 |
<p>The method consists of using the recovered bit rate signal to define a time window which overlaps the beginning, but not the end of each jitter range in the version of the digital train intended for use by the bit rate recovery circuit. Those transitions in said version of the digital train which occur during said window are then delayed by a fixed delay of duration less than the maximum peak-to-peak amplitude of the jitter. Other transitions are not delayed. The apparatus shown is intended to operate with a binary version I of the digital train and with a recovered bit rate signal H which is symmetrical and rectangular in shape with a first one its levels defining a time window which extends over the second half of each period in the digital train. The apparatus is essentially constituted by a pulse generator (10) which transforms the transitions in the binary version I of the digital train into pulses of duration tau equal to one-half of the maximum peak-to-peak amplitude of the jitter, a first D-type register (11) delaying transitions in the recovered bit rate signal (8) so that they lie outside the pulses generated by the pulse generator (10), and a second D-type register (12) which delays transitions in the binary version I to lie outside the periods when the recovered bit rate signal having possibly delayed transitions (J) is at its first level. The apparatus is entirely constituted by logic circuits and is easy to integrate.</p> |
