| 摘要 |
PURPOSE:To attain low power consumption operation without decreasing an operation limit frequency by using two data flip-flops and two 2-input/1-output basic logic gates so as to apply 2/3 variable frequency-division to two-modulus part of divided by 2<n>/2<n> 2-modulus prescaler. CONSTITUTION:When a mode switching signal (m) goes to a low level, the low level of an output q13 of an output terminal Q13 is read by a DFF 14, the output q14 of an output terminal Q14 goes to a low level and the inverse of an output q14 of the inverse of an output terminal Q14 goes to a high level. A DFF 13 reads a high level by using the inverse of an output q14 at the inverse of an output terminal Q14 going to a high level by the next clock pulse ck, the output q13 of an output terminal Q13 goes to a high level during a period T3, outputs q13, the inverse of q13 of output terminals Q13, the inverse of Q13 are operated at a period T2 and 1/3 frequency division waveform of a clock pulse is obtained. The divided by 2/3 variable frequency division is obtained depending on high/low level of the mode switching signal (m). A T flip-flop is connected to the 2-modulus part like this and 1/2 frequency division is applied for a proper number of times to obtain 2-modulus prescalers of divided by 64/65 and divided by 128/129. |
