| 摘要 |
PURPOSE:To attain the effective utilization of a central processor by bringing a part between a port of a central processor generating binary data for recording and a latch circuit connected to the port into a high impedance state substantially except at the superimposing period decided with a synchronous signal in a video signal. CONSTITUTION:A Q output (c) of a counter 5 and an output of an inverter 9 are ANDed by a AND gate 10 and its output (g) shows the data overlap period to the video signal. The output (g) of the AND gate 10 is fed to a CPU12 and a buffer 14 and the buffer 14 goes to a high impedance state at a period other than the data overlap period. Further, no rectangular wave is outputted from a 1/4 frequency divider 7 other than the data overlap period and a 4-bit latch and a shift register circuit 11 are inoperative, then ports X1-X4 of the CPU12 and the circuit 11 are in high impedance state substantially. Thus, the ports X1-X4 of the CPU12 and a port Y are usable other than the data overlap period. |
