| 摘要 |
<p>@ In a semiconductor memory device, a decoder circuit (1) is located between first (3) and second (5) memory cell arrays. A sequence of driver circuits (121,122...) in the decoder circuit (1) provides driver circuits common to the first and second memory cell arrays. An output terminal (1211 a,1211b,1221a,...) of each driver circuit is connected directly to a data input/output portion (2) for the first memory cell array (3) and connected to another data input/output portion (4) for the second memory cell array (5) via wirings (141 a, 141 b, 142a, ...) traversing the decoder circuit (1 ).</p> |
