| 摘要 |
PURPOSE:To simplify the operation for data transmission and to eliminate necessity for a high frequency for the transmission by providing an n-bit shift register/latch circuit with a memory function of parallel n-bits against one heating element. CONSTITUTION:The data is inputted to the shift register 1 as an information of 2<n> gradations (n=8 i.e. 256 gradations) in an n-bit-parallel form. A counter 7 receives the information in the shift register 1 as a preset data, and its data is held in the counter 7. The counter 7 starts counting down with a signal of CLK2, and excitens each heating body 5 for a length of time specified by the data which is an optional one of those in the register 1. In case n=8, 256 kinds of printing time can be specified individually against each heating body 5.
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