| 摘要 |
Each cell (C00 to C127, 127) is a one-transistor and one-capacitor type memory cell. Each memory cell (e.g. C00) is connected to one word line (WL0), to one bit line (BL0) and to one power supply line (WL0). The power supply line WL0 is controlled by a gate G'0. The potential of the power supply line WL0 can be controlled so as to fall and then rise so as to facilitate the storing of more charges in a capacitor of a memory cell by a boot strap effect. |
