| 摘要 |
PURPOSE:To shorten an idle state of an MPU by executing an address calculation of the second call processor instruction, a fetch of an operand data, etc., by the MPU, when a Co-Processor is executing the first call processor instruction. CONSTITUTION:When a Co-Processor executes the first Co-Processing instruction, and reaches a pre-fetch means, an MPU executes a pre-fetch of the second Co-Processor instruction. Also, the MPU executes a fetch of the second Co- Processor instruction which follows the first Co-Processing instruction, decoding, an address calculation of an operand, and a fetch of an operand data. When an end signal from the Co-Processor is received, the MPU transfers a data required for executing the instruction, to the Co-Processor. |
