| 摘要 |
PURPOSE:To shorten an activating time and to speed up vector processing by devicing a vector processing stated by codes separating a scalar instruction and a vector one with theory relating to a vector processor. CONSTITUTION:Scalar and vector processors are provided at every one of check counters 16, 17. The processors start weight and the check counters 16 and 17 are activated after contents are cleared to zero. Then counting is executed at every machine cycle. The count-up is stopped only when the processors attain weight release. If overflow occurs due to the count-up, the program stage language of the scalar processor is re-written and the control of the scalar is shifted to an interruption processing routine. |
