发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To array all the cell blocks without any unavailable region by a method wherein, in the arrangement structure of cell block according to a building block system, the number of the parallel arrangement stages of the polycell-structure arrays of each cell block is properly modified and the configurations of the respective cell blocks are prescribed. CONSTITUTION:When blocks B1-B9, in each of which plural pieces of polycell- structure arrays C1-C5 are arrayed in parallel to one another across each wiring region L, are arrayed, the number of the parallel stages of the polycell- structure arrays belonging to each block is properly modified and the configurations of the respective blocks are prescribed. For example, when a block 8 and a block 9 are arranged, the numbers of the parallel stages of the polycell-structure arrays of the blocks 8 and 9 are respectively modified for eliminating an unavailable region I2 to generate on the boundaries of both of the blocks 8 and 9 and a block 5 and the configurations of the blocks 8 and 9 are modified so as to fill the above-mentioned unavailable region. Hereby the unavailable region to generate between each blocks is activated and the utilization efficiency of the substrate can be improved.
申请公布号 JPS61229341(A) 申请公布日期 1986.10.13
申请号 JP19850070219 申请日期 1985.04.03
申请人 NEC CORP 发明人 AIZAWA HISAMITSU
分类号 H01L21/82;H01L27/02;(IPC1-7):H01L21/82 主分类号 H01L21/82
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