| 摘要 |
PURPOSE:To produce the overhead of a device and to perform logic simulation at a high speed by distributing equally the node load of a parallel logic simulator to processors. CONSTITUTION:Node data is stored in a storage part 100 of the parallel logic simulation device, and this node data is received by a node classifying part 200 to generate data of a node distribution for the level of each classification of nodes. A node-classified processor number determining part 300 which receives this node distribution data determines the number of processors to be simulated in accordance with each classification of nodes. This determined number of processors is received by a processor-classified node classification assigning part 400, and the classification of a node to be simulated is assigned to every received processor number and is supplied to a processor-classified node assigning part 500. The node load is equally distributed to processors 61-63 of a processor part 600 by a node assigning circuit 51 of the assigning part 500 to reduce the overhead of the device.
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