| 摘要 |
PURPOSE:To attain the control of the dual CPU without using any complicated arbitration circuit and share memory by holding one of the dual muCPU. CONSTITUTION:Both muCPU 1 and 2 work by means of local memories 5 and 6 which are asynchronous with each other. When the muCPU 1 transmits information to the CPU 2, the muCPU 1 delivers an access signal 7 to an arbitration circuit 3. The circuit 3 receives the signal 7 and delivers a holding request signal 17 to the muCPU 2 after confirming that no access signal 9 is delivered from the muCPU 2. Then the circuit 3 delivers a waiting signal 8 to the muCPU 1. The muCPU 2 receives the signal 17 and is set under a holding state to set a bus at a high impedance. Then the circuit 3 release the signal 8 to the muCPU 1, and the muCPU 1 can have an access to the memory 6. |
