| 摘要 |
PURPOSE:To prevent reduction in the execution speed with less number of components by generating a DMA request signal just before when one-chip CPU accesses a RAM of a main CPU and using a signal replying DMA enable from the main CPU so as to switch a bus. CONSTITUTION:A read or a write signal from the one-chip CPU is inputted and an HOLD signal with a prescribed width is generated after a prescribed time. When the one-chip CPU 1 sends the read signal RD or write signal WR, a monostable multivibrator 4a gives a delay of 6.5musec and a monostable multi-vibrator 4b sends a pulse of 2musec width. The pulse becomes the HOLD signal, which is sent to the main CPU. When the main CPU receives the HOLD signal, an HLDA signal being its reply is sent to a bus buffer to open the bus buffer 2, and the read signal RD or the write signal WR stopped by the bus buffer 2 is given to the main CPU as an MRD or an MWR respectively and the one- chip CPU 1 can access directly the data of the RAM used by the main CPU. |
