| 摘要 |
<p>An apparatus for testing semiconductors such as LSI's, comprising low-speed large-capacity memories (11 to 14) that undergo interleaving operation, and a high-speed small-capacity memory (50) in which are stored, in advance, test patterns after the branching. The test patterns are successively read out from the low-speed large-capacity memories (11 to 14). When the order of reading is branched, the high-speed small-capacity memory (50) is selected. The test patterns are read out from the high-speed small-capacity memory (50) until they can be read out again from the low-speed large-capacity memories (11 to 14), such that a tremendous number of test patterns can be produced without generating dummy cycles.</p> |
