CACHE INVALIDATION MECHANISM FOR MULTIPROCESSOR SYSTEMS

摘要

There is disclosed, for use in a digital computer system having a common communications path interconnecting a plurality of devices, including devices having local memory accessible without use of said path and cache memory for storing data communicated over said path from said local memory, the improvement which comprises a device which maintains the integrity of cached data, the device including: means for selectively registering accesses on the path to the local memory by devices having cached memory associated therewith, and means responsive to the registering means for notifying cached memory devices of non-path accesses to the local memory.