发明名称 DATA PROCESSOR
摘要 PURPOSE:To attain the highly efficient execution of an operation between data designated from the areas having different bit widths of addresses, by adding a part to an area storing addressed to indicate the address bit width. CONSTITUTION:The contents read out of a general-purpose register by an indication of a data line 24 are sent to a ''0'' detecting circuit 41 which calculates the length of a desired address area from the number of ''0'' continuous from the highest place as well as to a left-shifter 44 which inserts ''0'' from the right side. The register 44 is used to secure the matching of position between the lowest bit of the data given fro a GPR and the lowest bit of an address area within a main memory in response to the output of the circuit 41. While an OR gate group 48 is used for addition of the upper address bit width information contained in the address expression.
申请公布号 JPS61136144(A) 申请公布日期 1986.06.24
申请号 JP19840257512 申请日期 1984.12.07
申请人 HITACHI LTD 发明人 TORII SHUNICHI
分类号 G06F12/02;G06F12/06 主分类号 G06F12/02
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