| 摘要 |
PURPOSE:To simplify the hardware and to improve the expanding performance of a line to be supported by connecting a virtual port comprising a read/write memory at any time to a bus to which a port being an interface with a terminal device is connected. CONSTITUTION:The internal bus 141 connecting the terminal interface (port) 15 is provided with the virtual port 17 comprising a read/write memory at any time. In case of relaying also, the data transmitted from a high speed line 111 is written once in the port 17, and then the said data is read at any time and transmitted from other high speed line 112, which is controlled by time division multiplex control sections 131, 132. Thus, the internal bus connecting directly the control sections is abolished to simplify the hardware of the titled device and improve the expanding performance of the lines to be supported.
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