| 摘要 |
PURPOSE:To make small a scale of a hardware by connecting outputs of the first three state logic elements and outputs of a pair of the second three state logic elements by a pair of relating data lines. CONSTITUTION:If a processor 12-0 is a present system, the first three state logic element 22-0 is conductive by an ACT signal, while at a preliminary system of a processor 12-1, an output of the first three state logic element 22-1 becomes high impedance. Thereby, a wired OR of the output between both the elements 22-0 and 22-1 can be done, through one relating data line 25-1, a control data DT can be transmitted to a network body 16 from a circuit 21-1. The first AND gate 24-0 in which a coincidence signal M' corresponding to a response data DT' rises and receiving an ACT signal makes the second three state logic element 23-0 conductive and transmits the response data DT' to the processor 12-0. |
